1. Field of the Invention
The present invention relates to a silicon layer with high resistance and a fabricating method thereof.
2. Description of the Related Art
In an integrated circuit process, a silicon layer plays an important role, especially in an application to a gate of a metal oxide semiconductor (MOS) or an interconnect structure. Generally speaking, the fabrication method of a silicon layer is to perform a chemical vapor deposition (CVD) process to form a silicon material layer, followed by performing an ion implantation process to implant dopants therein for increasing conductivity of the silicon material layer.
It is noted that the conductivity of the silicon layer is related to the amount of the dopants implanted therein. In general, if we want to fabricate a silicon layer with high resistance, the amount of dopants implanted must be decreased. However, when the amount of the implanted dopants becomes less, variations of the conductivity between silicon layers become larger. Since these silicon layers are fabricated with the same implantation process, but on different wafers, the reliability of devices containing these silicon layers is poor.